1. Field of the Invention.
The present invention relates to a method for balancing the current distribution to a plurality of switching devices of a full-bridge inverter, such as a power supply for induction heating used in hardening or tempering members. The full-bridge inverter has each arm equipped with a plurality of parallel connected switching devices and is composed of two bridge portions comprising a plurality of module-type circuits. That is, the integrated modules with corresponding switching devices in both arms form a half bridge and are connected to each other.
2. Description of the Prior Art.
Inverters may include a plurality of parallel connected switching devices in each arm in order to increase output power.
In such an arrangement, a method has been available in which an equidistant, or mechanically symmetrical, arrangement is provided to obtain a constant wiring inductance to the load via each switching device from a DC power supply to thereby secure a balance of currents supplied to each switching device.
For instance, a book entitled "Power Electronics" by Fouji Imai, published by DENKI SHOIN CO., LTD. in 1977 illustrates an equidistant wiring arrangement in FIG. 2.33 at Page 63 of SECTION 2.5.2 "Parallel Connection".
There are increased demands for relatively small output full-bridge inverters in which each arm includes a single switching device.
Modules which integrate two series connected switching devices to obtain a half-bridge inverter are marketed at a low cost in great quantities due to their convenient usage.
In attempting to form a half-bridge inverter using such inexpensive modules connected in parallel to obtain a greater output level at a low cost, extreme difficulties will arise in creating the equidistant wiring or mechanically symmetrical arrangement due to the configuration of the integrated modules, resulting in a possible imbalance of current distribution.
FIG. 1 is a basic circuit diagram of a full-bridge inverter in which transistors are used as the switching devices.
As shown in FIG. 1, A to D denote the arms of the full bridge inverter connected to load Lo, Sa1 to Sa3 denote the parallel connected switching devices comprising arm A, Sb1 to Sb3 denote parallel connected switching devices comprising arm B, Sc1 to Sc3 denote the parallel connected switching device of arm C, and Sd1 to Sd3 denote the parallel connected switching devices comprising arm D.
Inverters as showing FIG. 1, as is known to the art, are capable of having input thereto a DC current from a power supply and outputting an AC current to load Lo by alternation of simultaneous conductions of switching devices Sa1 to Sa3 in arm A and switching devices Sd1 to Sd3 in arm D, and simultaneous conductions of switching devices Sc1 to Sc3 in arm C and switching devices Sb1 to Sb3 in ar B.
FIG. 4 illustrates a conventional arrangement in which a plurality of modules, each having two integrated series connected switching devices, for example Sa1 and Sb1, are connected to feed bars and output bars.
In FIG. 4, SB+ and SB- denote positive and negative terminal feed bars respectively connected to a DC power source (not shown), OB1 and OB2 denote output bars connected to load Lo, MA1 to MA3 denote the modules forming one half-bridge of the inverter and MD1 to MD3 denote the modules forming another half-bridge of the inverter.
The connecting arrangements of FIG. 4 of the modules is intended to realize the equidistance requirements at least as closely as possible by inverting the DC power source side of the feed bars and the load Lo side of output bars, and by arranging symmetrically the MA side and the MD side.
However, it has become clear during studies made in finalizing the present invention that the arrangement of FIG. 4 does not provide a balanced conduction of the current through each switching device.
The above-noted conduction of current imbalance will be appreciated by the following description. Reference is first made to switching device Sa1. The loops formed by current ia1 flowing through switching device Sa1 include loop MA1-MD1, consisting of SB+.fwdarw.Sa1.fwdarw.OB1.fwdarw.Lo.fwdarw.OB2.fwdarw.Sd1.fwdarw.SB-, and another two loops sharing the same outgoing path but having different return paths out of load Lo, i.e. loops MA1.fwdarw.MD3 via Sd2 and MA1.fwdarw.MD3 via Sd3.
The wiring inductances of these loops are discussed below, except for the line inductance of the circuit because the modules are arranged equidistance to each other and each loop requires both the circuit between the power source and each module and the circuit between each module and the load Lo.
Wiring inductances L of each loop are:
MA1-MD1--1L PA0 MA1-MD2--2L PA0 MA1-MD3--3L
where L is a wiring inductance between each module with the arranged position of switching device Sa1 included in module MA1 as reference.
The current tends to flow along the route of the smallest current-conducted area as wiring inductance L varies proportionally with current-conducted area. Accordingly, the relative values of currents ia1.fwdarw.d1, ia1.fwdarw.d2 and ia1.fwdarw.d3 flowing in a loop to MD1, MD2 and MD3 via MA1 are: EQU ia1.fwdarw.d1=1 EQU ia1.fwdarw.d2=1/2 EQU ia1.fwdarw.d3=1/3
where the value of current ia1.fwdarw.d1 is 1.
Similarly, wiring inductances L of the loop formed with switching device Sa2 included in MA2, and the loop formed with switching device Sa2 included in MA2, and the loop formed with switching device Sa3 included in MA3, together with the case of MA1 with loop MA1-MD1 as the base position, and relative current values flowing each loop when the value of current ia1.fwdarw.d1 is 1, are given in TABLE 1.
TABLE 1 ______________________________________ Loops formed Wiring induc- Current values Re- Modules tances of each flowing through ference on return loop as each loop modules side MA1 - MD1 = 1L as ia1 .fwdarw. d1 = 1 ______________________________________ MD1 1L ia1 .fwdarw. d1 = 1 MA1 MD2 2L ia1 .fwdarw. d2 = 1/2 MD3 3L ia1 .fwdarw. d3 = 1/3 MD1 2L ia2 .fwdarw. d1 = 1/2 MA2 MD2 3L ia2 .fwdarw. d2 = 1/3 MD3 4L ia2 .fwdarw. d3 = 1/4 MD1 3L ia3 .fwdarw. d1 = 1/3 MA3 MD2 4L ia3 .fwdarw. d2 = 1/4 MD3 5L ia3 .fwdarw. d3 = 1/5 ______________________________________ The sum totals of current values flowing through each switching device included in modules MD1 to MD3 on the return path, i.e. Sd1, Sd2 and Sd3, are: EQU Sd1; 1+1/2+1/3.congruent.1.83 EQU Sd2; 1/2+1/3+1/4.congruent.1.08 EQU Sd3; 1/3+1/4+1/5.congruent.0.75,
resulting in significant differences (as high as 41%) in the current distributions and in concentrated currents flowing inside module MD1 as seen from the Table 1.
The above calculation is also applicable to the loop resulting where model MA1 to MA3 is made a return path, i.e. the loop with switching devices Sc1 to Sc3 as the return path, and the more the number of modules there are, the more intensive the concentration of current becomes in the innermost switching device due to the summation of tiny differences in the wiring inductance L produced in each loop, resulting in a large inbalance in the current distribution.
Inbalance in current distribution may cause open-circuit or short-circuit faults due to overload of switching device to which the current is concentrated.
For instance, if a switching device is open-circuited the other switching devices in the same arm will take over for the failed device and maintain the output power so that the inverter is kept running without notice of the fault. Then, once one switching device fails, the other switching devices in the arm become overloaded, resulting in a chain reaction of troubles.
A short-circuited switching device may make the inverter operation instable, and if the inverter is kept running without notice of the fault, the circuit of the failed device will be broken due to overheating, thus triggering a chain reaction of troubles in the other switching devices in the arm similar to the above open-circuit fault situation. Thus, the conventional method has not been capable of avoiding the spread of damages due to a single faulty device, regardless of whether the fault is a open-circuit or a short-circuit.